Challenge and Response -- Thermal and Power Analysis in 3DIC Design
As the Moore’s law approaching the physical limit of the critical size on chip, designers are now targeting at building devices in the third dimension, namely, out of the plane where the chip sits. This so-called 3DIC configuration presents a heterogeneous, disaggregated structure where multiple chiplets can be stacked up and placed on a common substrate or interposer. Due to the structural complexity and critical interface connections, the 3DIC design has become the main R&D focus among advanced IC chip designers and foundries alike. Furthermore, when integrating multiple heterogeneous components on one substrate, the designers quickly realize the thermal interaction and temperature distribution among those components under various power sources is one of the gating factors for achieving the desirable performance with optimization.
In this talk the challenges of 3DIC designs from the thermal and power aspects will be briefly addressed, based on the 3DIC configurations presently surfacing in the public domain. Inevitably multi-physics simulation is essential to obtain clear and in-depth understanding of such a complex system, including both steady and transient states analyses based on electrical-thermal co-simulation, Computational Fluid Dynamics (CFD) simulation, IC level power analysis, and so on. Then the ultimate challenge will be to combine these physical simulation modules, forge a holistic solution, and provide the accurate and efficient tool set as the industry advancing into this 3DIC era.
Registration link:
Speaker Bio
C. T. Kao is currently focusing on the R&D of multi-physics analysis products of Physim Electronic Technology. Before joining Physim, he was the Solution Architect of thermal and power analyses of the tool Integrity 3D-IC announced by Cadence in October of 2021. Prior to Integrity 3D-IC, he was responsible for the product development and management of the tool Celsius which Cadence launched in late 2019. C. T. has been performing analysis, simulation, and product design in the fields of electronic packaging, semiconductor processing equipment, and Micro-Electro-Mechanical Systems (MEMS) for more than 20 years. He previously also worked for National Semiconductor (acquired by Texas Instruments) in the Packaging Technology Group and for Applied Materials in designing semiconductor components and equipment for physical vapor deposition (PVD) and atomic layer deposition (ALD) processes. C. T. received his B.S. from National Taiwan University and M.S. from the University of Texas at Austin, both in Mechanical Engineering, and his Ph.D. from Stanford University in Aeronautics and Astronautics.
